[3] KNL1-100 Residual Current Circuit Breaker
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With the rapid development of CMOS technology, CMOS image sensors have been widely used in the field of image acquisition such as ultra-miniature digital cameras and mobile phones due to their high integration, low power consumption and low cost. Pipeline analog-to-digital converters are widely used in chip-level and column-level A/D converters for image sensors due to their high speed, low power consumption, and high precision. Currently, the pipelined A/D converter has reached a mature international level of 14 bit 10 MHz. Most of the successful domestic chips are 10 bit pipeline A/D converters, so more than 10 bit high precision pipelined A/D converters need further research. In the A/D converter, the sample-and-hold circuit is the most critical module of its front end, and its performance directly determines the performance of the entire ADC.
This paper uses a fully differential charge-transfer structure of the sample-and-hold circuit, which can eliminate the charge injection and clock feedthrough independent of the input signal; eliminate the charge injection associated with the input signal through the bottom plate sampling technique. And clock feedthrough; use the gate voltage bootstrap circuit to eliminate the nonlinearity of the switch. A folded gain-enhanced operational amplifier is also used to reduce errors due to finite gain and incomplete setup. The sample-and-hold circuit has a spurious-free dynamic range (SFDR) of 76 dB and a sampling accuracy of 0.012% at a 5 V supply voltage and 20 MS/s sampling frequency when the input signal is at the Nyquist frequency. Precision requirements.
1 sample and hold circuit
FIG. 1 is a sample-and-hold circuit structure designed herein, which is called a charge transfer type sample-and-hold circuit.
Its working timing is shown in Figure 2. clk1 and clk2 are two-phase non-overlapping clocks. The control sample-and-hold circuits operate in the sample phase and the hold phase respectively; clkb is the inverse of clkl. When clk1 is high, the circuit enters the sampling phase, the two input terminals of the op amp are short-circuited, and the input signal is stored in the sampling capacitor Cs; when clk2 is high, the circuit enters the holding phase, and the differential charge is transferred to the feedback capacitor Cf. .
In the process of maintaining the phase transition from the sampling phase, clklpp, clklp, and clkl are sequentially turned off, and the bottom plate sampling is realized to reduce the influence of the switching clock feedthrough and the channel charge injection; and only the differential charge is transferred to the feedback capacitor Cf. Above, the common mode charge is always stored on the sampling capacitor Cs. Therefore, this structure can handle input signals with a large common mode range.
2 sampling capacitor, switch selection and design
2.1 Selection of sampling capacitor
In the sample-and-hold circuit, the value of the sampling capacitor has a direct impact on the performance of the circuit. The smaller the sampling capacitance, the larger the thermal noise, because the thermal noise is mainly generated by the on-resistance of the switch in the circuit, and the variance is a function of the value of the switched capacitor (σ 2 thermal ≈kT/C, where k is the Boltzmann constant, When T is absolute temperature, the signal-to-noise ratio (SNR) of the circuit is reduced. If the sampling capacitance is large, the power consumption of the circuit will increase and the speed will be slow. At this time, the signal-to-noise ratio is mainly limited by the quantization noise, and there is no significant improvement. Therefore, in the design, the noise is limited to a certain range, the minimum value of the capacitor is obtained, and then some power consumption and speed are sacrificed, and a slightly larger capacitance value can be obtained. The ADC designed in this paper has a 12-bit resolution with a quantization range of ±1 V. If the SNR caused by thermal noise and quantization noise is required to drop by up to 1 dB, it is necessary to satisfy: kT/Cs < Δ 2 / 46.3, and Δ is the amplitude corresponding to 1 LSB. According to the above formula, the sampling capacitor Cs>0.8 pF, and Cs=Cf=1 pF.
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0 Preface
May 22, 2023