ADSP-SC57xSHARC Dual Core Processor Solution (Characteristics, Block Diagram, Circuit Diagram)

ADI's ADSP-SC57x/2157x family of processors integrates two enhanced SHARC+® cores and advanced DSP accelerators (FIR, IIR) that consume less than 2W and are more than five times more powerful than previous SHARC products. Designed for applications that require a DSP coprocessor and includes two SHARC+ cores and a peripheral set that matches the DSP core, primarily used in automotive, consumer electronics and professional audio, multi-axis motor control and energy distribution systems. This article describes ADSP- SC57x/ADSP-2157x System Features, Processor Block Diagram, ARM Cortex-A5 Processor Block Diagram, SHARC Processor Block Diagram, SHARC+SIMD Processor Core Block Diagram and Evaluation Board ADSP-SC573 EZ-KIT Key Features, Block Diagram, Circuit Diagram and Materials Checklist.

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC® family of products. The ADSP-SC57x processor is based on the SHARC+® dual-core and the ARM® Cortex®-A5core. The ADSP-SC57x/ADSP-2157x SHARC processors Aremembers of the single-instrucTIon, mulTIple data (SIMD) SHARC family of digital signal processors (DSPs) that featureAnalog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floaTIng-point processors are opTImized for high performanceaudio/ Floating-point applications with large on-chipstatic random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovativedigital audio interfaces (DAI). New additions to the SHARC+core include cache enhancements and Branch prediction, whilemaintaining instruction set compatibility to previous SHARC products.

By 。 。 。 。 。 Span a wide array of markets, including automotive,professional audio, and industrial-based applications thatrequire high floating-point performance.

ADSP-SC57x/ADSP-2157x System Features:

Dual-enhanced SHARC+ high performance floating-pointcores
Up to 450 MHz per SHARC+ core
Up to 3 Mb (384 kB) L1 SRAM memory per core with parity(optional ability to configure as cache)
32-bit, 40-bit, and 64-bit floating-point support32-bit fixed point
Byte, short word, word, long word addressed
ARM Cortex-A5 core
450 MHz/720 DMIPS with NEON/VFPv4-D16/Jazelle
32 kB L1 instruction cache with parity/32 kB L1 data cachewith parity
256 kB L2 cache with parity
Powerful DMA system
On-chip memory protection

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