Detailed DRAM based on VLT technology

OFweek VerTIcal Layered Thyristor (VLT) is a new memory unit developed by Kilopass that significantly reduces the cost and complexity of dynamic random access memory (DRAM). This is a static memory unit that does not require a refresh operation; it is compatible with existing fab manufacturing equipment and does not require any new materials or processes.

VLT memory arrays can save up to 45% in cost compared to general DRAM; this is because it has smaller VLT memory cells and the ability to drive longer rows and columns, which greatly increases memory array efficiency. However, in order to take advantage of VLT, it is necessary to design and manufacture in the mature DRAM market based on industry standards to ensure compatibility with memory products from different vendors.

Currently, VLT-based memory is fully compatible with the existing "fourth generation low power double data rate" (LPDDR4) specification. The VLT memory bank can emulate the bank of a traditional DRAM and is compatible with its frequency; when designing a VLT circuit, the designer can choose to connect a standard DDR controller or a lower cost simplified controller. If a standard controller is used, the VLT memory will ignore the refresh sequence because no refresh is required. The rest of the system will treat VLT DRAM as general purpose DRAM, so no changes are required.

To show how to construct LPDDR4 memory using VLT memory cells, let's first review how traditional DRAM and LPDDR4 work. Those who are familiar with DRAM may have some understanding of it, but there are still some slight differences in practical application. Here, some guidelines and terms are defined to facilitate understanding.

Many aspects of DRAM operation depend on its capacitive storage unit. First, the leakage characteristics of the capacitor lead to the necessity of refreshing; secondly, one of the basic operations of the storage unit is reading, which affects how other aspects of memory are organized.

Figure 1 shows the schematic of the capacitor storage unit. The left and right diagrams represent reading 1 and reading 0, respectively. The circuit detects the memory bit value through "charge sharing". The bitline is first precharged to a voltage between 0 and 1, and then a memory cell is selected by turning on the read transistor so that charge can flow between the bit line and the memory cell. If the bit line voltage is higher than the memory cell, the negative charge will flow out of the memory cell to the bit line; if the bit line voltage is lower than the memory, then the negative charge will flow from the bit line into the memory cell.

Figure 1: Principle of charge distribution for a conventional capacitive DRAM memory cell (the green arrow in the figure shows the current, opposite to the direction in which the negative charge flows)

This charge transfer changes the voltage at the bit line and the final read value is obtained by sensing and latching. However, the charge lost or acquired in the storage capacitor changes the original charge on the node, which means that the process of reading is destructive. Therefore, after each read, the charge in the memory cell must be recovered by a write-back operation.

The LPDDR4 standard is the low-power version of the fourth-generation double data rate (DDR) DRAM. It defines the high-level structure of individual memory chips and how to arrange dual in-line memory modules (DIMMs) through the overall architecture.

There are two general ways to analyze DRAM: in theory, the physical details are analyzed; in fact, it focuses on the characteristics of its chip array. This article first explores the first logical point of view, because all physical layouts must be broken down into the same logical structure, so that we can understand how traditional DRAM and LVT approaches implement logic functions.

The LPDDR4 memory chip has 8Gb of storage capacity and is usually composed of two 4Gb independent channels. Each channel has 8 memory banks, each memory bank includes 32K pages, each page has 16K bits, and the total capacity of the memory group reaches 512Mb.

Figure 2: Typical DRAM architecture and hierarchy

A complete LPDDR4 memory chip consists of two high-level units: a memory array and a DDR interface. Some parts of the operation will affect the memory array; the other part will affect the interface. The DDR interface can communicate with both the memory array and the external system.

Figure 3: The logical organization of LPDDR4, which separates the storage array from the DDR interface. (arrows represent a read operation and write back)

Figure 3 illustrates this relationship, namely the DDR buffer as the primary interface between the external system and the memory array. When reading data, the array data is first loaded into the DDR buffer; when writing, the required data is first written to the buffer from the outside.

Since reading the contents of the conventional DRAM array may destroy the original data, a write back operation must be performed after each read to restore the original value. After reading, the contents of the DDR buffer are copied into the "Shadow Register". When the external system reads the data in the DDR buffer, the hidden buffer is responsible for writing the data back to the selected page to restore the original value. Similarly, when data is written, the DDR buffer data is transferred to the hidden buffer for writing; while the write job is being executed, the DDR buffer can load new data.

Reading memory paging data involves a series of activities, similar to two nested software DO loops. Each paged memory is divided into memory groups that are read by many 256-byte bursts. Therefore, a group of 16K-bit pages has 64 burst memory groups, which sequentially read the complete memory pages. This is similar to an external DO loop.

Figure 4: Memory paging consists of memory groups read sequentially in batches; each batch of burst groups is transferred to I/O based on 16 consecutive 16 bits.

Each burst transfer group is loaded into a 256-bit DDR buffer, which is divided into 16 16-bit words and sequentially reads its contents, providing each 16-bit word for each frequency edge. This mode of operation is like an internal DO loop.

The address of each line (RAS) is responsible for selecting the paging. At the same time, the address of each column (CAS) selects the burst transfer group and sets the characters to be read from the DDR buffer, so it is not necessary to start reading from the left side of the DDR buffer.

It is worth noting that while the hidden buffer performs the write back, read or write DDR buffer to load the data, the DDR buffer has begun to read data from the storage array or externally load the written data.

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