This article mainly refers to "MICRO CONTROLLER DESIGN GUIDELINES FOR ELECTROMAGNETIC COMPATIBILITY". Although this article was written many years ago, it has many very practical reference meanings. In addition, other IC manufacturers also have a lot of reference documents. If you are interested, you can refer to them. Digression, write this topic is to analyze the main internal sources of interference and sensitive components in the module, through the design of these major things to gradually experience the module's EMC design, but it is difficult to avoid some suspicion, accumulate more likely in the future design When the circuit is in the early stage, it is easy to consider the problem thoughtfully and meticulously. 1, the working frequency of the one-chip computer 1.1, the design of the SCM should be based on the needs of customers to choose a lower operating frequency First introduce the advantages of doing so: using a low crystal and bus frequency allows us to choose a smaller microcontroller to meet the timing requirements, so that the operating current of the microcontroller can become lower, the most important is the peak current of VDD to VSS smaller. Of course, we need to make a compromise here, because the customer's requirements may be compatible and platform-based (current trend of automotive electronics is the platform), select a higher operating frequency can be compatible with more platforms, but also facilitate future upgrades and Extended, so choose a lower acceptable operating frequency. 2, the appropriate output drive capability Given a load specification, rise and fall times, and proper rise time of the output, minimizing peak currents in the output and internal drivers is one of the most important design considerations for reducing EMI. Unmatched drive capability or control over the rate of change of the output voltage may result in impedance mismatch, faster switching edges, overshoot and undershoot of the output signal, or power and ground noise. 2.1. Design the output driver of the SCM, first determine the load, rise and fall time of the module, output current and other parameters. According to the above information drive capability, control the voltage slew rate. Only in this way can we meet the module requirements and meet the EMC requirements. . The higher edge rate that the driver can produce than the actual required charging speed, will have two disadvantages: 1. The harmonic content of the signal has increased. 2. With load capacitance and parasitic internal bonding lines, IC package, PCB inductance together, will cause the signal on the punch and undershoot. Choosing the right di/dt switching characteristics can be achieved by carefully selecting the size of the drive capability and controlling the voltage slew rate. The best choice is to use a load-independent constant voltage slew rate output buffer. The same pre-driver output voltage slew rate can be reduced (ie, rise and fall times can be increased), but the corresponding propagation delay will increase, and we need to control the total switching time). 2.2, using the programmable single-chip output drive capacity to meet the actual load requirements of the module. The simplest parallel output driver for the programmable output port is the Rdson of their MOS. The output current capability is also different. We can choose different modes when testing and actually using. Actually the current microcontrollers generally have at least two modes to choose from, and some may even have three (strong, medium, and weak). 2.3 When the timing constraint has enough margin, slow down the internal clock driven edge by reducing the output capability. Reducing the peak current of the synchronous switch, and di/dt, an important consideration is to reduce the ability of the internal clock drive (in fact, the amplification factor, the punch-through current is associated with a large type). Lowering the clock edge current will significantly improve EMI. Of course, the disadvantage of this is that the average current of the microcontroller may increase due to the longer turn-on time of the clock and the load. Fast edges and relatively high peak currents, and longer time edges and slower current pulses both require a compromise. 2.4. The internal drive (inverter) of the crystal oscillator should not exceed the actual requirement. This problem has actually been discussed in the past. When the gain is too large, it will cause even greater interference. 3, the design of the smallest through-current drive 3.1, Clock, Bus, and Output Drivers Should Minimize Conventional Current Through current [overlap current, short circuit current] is the current from the power supply to the ground when the PMOS and NMOS are turned on during the switching process of the single-chip microcomputer. The through current directly affects the EMI and the power consumption. This content is actually inside the microcontroller, the clock, the bus and the output driver. The way to eliminate or reduce the punch-through current is to turn off one FET first and then turn on one FET. When the current is large, additional pre-driver circuits or voltage slew rates are required. 4, the clock generation and distribution 4.1 As far as the microcontroller is concerned, we prefer to allocate clocks (smallest high-frequency clocks) to each section. Of course we need to manage the clock skew work. This is much better than using a large clock buffer that drives the entire IC clock. The synchronous CMOS design generates a large peak current at the clock edge. The use of the clock tree architecture (under system clock conditions) will reduce the synchronous switch current compared to the master clock driver and clock distribution circuitry. [Inherent delay time in the clock tree structure makes the switch separate at different times] 4.2. Use power management technology. Place the clock source as close as possible to the desired IC if you need to distribute the clock within a module. When the clock is not needed, turn off the clock source. In the sleep mode, you usually need to switch clocks. 4.3. Non-overlapping clocks should be used as far as possible under the system's limitations. Non-overlapping clocks are clocks that have no synchronization edges. From a system perspective, non-overlapping clock edges help eliminate competitive adventure and metastability. From EMC's point of view, the transition time between the added clock edges reduces the peak amplitude of the peak current and harmonics. The average current will remain roughly the same over time, but the amplitude and spectral shape will change. If the transition between the clocks is close but not synchronous (assuming the edge speed is much faster than the clock period), the current waveform will flatten and the duration will become longer. As the transition time increases, the current waveform will split into several pulses for each edge. The lower pulse amplitude correspondingly reduces the spectral magnitude of the harmonics, and the current pulse edges are likely to remain approximately the same (sustain pulse bandwidth). Ideally, the non-overlapping duty cycle in a two-phase system is 33%, maximizing the time between clock edges. However, it is impossible to use this method in practical applications. Some compromises must be made. The actual system does not allow such a large span of clock edges. 4.4. Keep the clock circuit away from the I / O logic circuit as much as possible to reduce the possibility of common mode radiation problems. The clock signal needs to stay away from I/O logic or parallel leads. The clock's transient edge can be coupled to the I/O logic to generate voltage noise. 4.5. The input pin synchronizer moves away from the microcontroller pin area and enters the core module of the microcontroller. This method can reduce the size of the required clock driver, Moving the synchronizer close to the clock source can reduce the length of the clock signal line. The capacitive load on the clock driver depends in part on the parasitic capacitance of the leads, and the clock-driven charge load will become smaller. Live Pro Speaker,8 Woofer Speaker,8 Inch Woofer Speaker,Woofer Speaker 8 Inch Guangzhou Yuehang Audio Technology Co., Ltd , https://www.yhspeakers.com
March 26, 2023