Detailed analysis of IC front-end design (logic design) and back-end design (physical design)

The distinction between IC front-end design (logical design) and back-end design (physical design):

The design distinguishes whether the design is related to the process; from the design perspective, the result of the front-end design is to obtain the gate-level netlist circuit of the chip.

Front-end design process and EDA tools used

1. Architecture design and verification

According to the requirements, the module is divided into the overall design. The simulation of the architectural model can use Synopsys' CoCentric software, which is a System C-based simulation tool. 2, HDL design input

Design input methods include: HDL language (Verilog or VHDL) input, circuit diagram input, and state transition diagram input.

The tools used are: Active-HDL, and the RTL analysis checker has Synopsys' LEDA. 3. Pre-simulation tool (function simulation)

Initially verify that the design meets the specifications.

The tools used are: VCS from Synopsys, ModelSim from Mentor, Verilog-XL from Cadence, and NC-Verilog from Cadence. 4, logic synthesis

Convert the HDL language to a gate-level netlist Netlist. The comprehensive need to set the constraints, that is, the standard that you want the integrated circuit to achieve on the target parameters such as area and timing; the logic synthesis needs to specify the library based on it, using different integrated libraries, there will be differences in timing and area. The simulation before logic synthesis is the pre-simulation, and the subsequent simulation is the post-simulation.

The tools used are: Synopsys' Design Compiler, Cadence's PKS, and Synplicity's Synplify. 5, static timing analysis tool (STA)

In terms of timing, it is checked whether the setup time and the hold time of the circuit are Violation.

The tools used are: Prime Time of Synopsys. 6, formal verification tools

Functionally, the integrated netlist is verified. Commonly used is the Equivalence Check method, which is based on the functionally verified HDL design. Compared with the integrated netlist function, whether they are functionally equivalent. This is done to ensure that the circuit functions described by the original HDL are not changed during the logic synthesis process.

The tools used are: Synopsys' Formality

Back-end design process and EDA tools used

Data preparation

For CDN's Silicon Ensemble, the data required for the back-end design is mainly the standard unit, macro unit and I/O Pad library files provided by Foundry. It includes physical library, timing library and netlist library, respectively. Given in the form of lef, .tlf, and .v. The front-end chip design is synthesized to generate a gate-level netlist, a script file with timing constraints and clock definitions, and a resulting .gcf constraint file and a DEF (Design Exchange Format) file that defines the power pad. (For Synopsys' Astro, the STP is the same as the gate-level netlist generated after the synthesis. The Pad definition file --tdf , .tf file --technology file, the standard unit and macro provided by Foundry The library file of the unit and I/O Pad is given in the form of FRAM, CELL view, LM view (Milkway reference library and DB, LIB file). 2. Layout planning

Mainly the layout of standard cells, I/O Pads and macro cells. The I/OPad gives the position in advance, while the macro unit is placed according to the timing requirements. The standard unit gives a certain area that is automatically placed by the tool. After the layout is planned, the size of the chip, the area of ​​the Core, the form of the Row, the Ring and the Strip of the power and ground are all determined. If it is necessary to automatically place the standard unit and the macro unit, you can do a PNA (power network analysis)--IR drop and EM .3.Placement - automatically place the standard unit

After the layout is planned, the location of the macrocell, the I/O Pad, and the area where the standard cells are placed are determined. The information SE (Silicon Ensemble) is passed to the PC (Physical Compiler) through the DEF file, and the PC is given by the synthesis. The DB file obtains netlist and timing constraint information for automatic placement of standard cells, while performing timing checking and cell placement optimization. If you are using PC + Astro then you can use write_milkway, read_milkway to pass data. 4. Clock Tree Generation (CTS Clock tree synthesis)

The clock network in the chip drives all the timing units in the circuit, so the clock source terminal unit is loaded a lot, its load delay is large and unbalanced, and the buffer needs to be inserted to reduce the load and balance delay. The clock network and the buffers on it form the clock tree. It is usually repeated several times to make an ideal clock tree. ---Clock skew.5. STA static timing analysis and post-simulation

After the clock tree is inserted, the position of each unit is determined. The tool can propose the connection parasitics parameters in the form of Global Route. At this time, the extraction of the delay parameters is more accurate. SE passes the .V and .SDF files to PrimeTime for static timing analysis. After confirming that there are no timing violations, pass the two files to the front-end personnel for post-simulation. For Astro, after the detail routing, with the starRC XT parameter extraction, the generated EV and .SDF files are passed to PrimeTime for static timing analysis, which will be more accurate. 6. ECO (Engineering Change Order)

For the problems in static timing analysis and post-simulation, a small range of changes to the circuit and cell layout. 7. Filler insert (padfliier, cell filler)

Filler refers to the logic-independent filler defined in the standard cell library and the I/O Pad library. It is used to fill the gap between the standard cell and the standard cell, and between the I/O pad and the I/O pad. It is to connect the diffusion layers to meet the DRC rules and design needs. 8. Routing (Routing)

Global route--Trackassign --Detail routing--Routingoptimization Wiring refers to the connection relationship of the circuit under the condition that the process rules and wiring layer limit, line width, line spacing limit and reliable insulation of each line network are satisfied. Connect the cells and the I/O Pad with interconnects, which are performed under Timing driven conditions to ensure minimum wire length on critical timing paths. --Timing report clear9. Increase of Dummy Metal

The Foundry plant has a specification for the density of the metal so that its metal density does not fall below a certain value to prevent over-etching of the metal layer of the wiring during the etching phase of the chip manufacturing process to reduce the performance of the circuit. Dummy Metal was added to increase the density of the metal. 10. DRC and LVS

DRC is a design rule (spacing, width) for each layer of physical graphics in the chip layout. It also includes an antenna effect check to ensure that the chip is normally streamed. LVS mainly compares the layout and the circuit netlist to ensure that the layout circuit from the stream is consistent with the circuit actually needed. DRC and LVS inspection - EDA tool Synopsy hercules / mentor calibre / CDN Dracula. Astro also include LVS/DRCcheck commands.11. Tape out

The final layout GDSII file was passed to Foundry for mask fabrication with all inspections and verifications in place.