With the development of CCD technology, new CCD cameras with high frequency and digitization have emerged. The digitization of the CCD camera output simplifies the interface design of the camera and transmission acquisition system, making the digital CCD camera more and more a detector in real-time PCI control, data acquisition, graphic image processing, remote sensing telemetry and other systems. This kind of CCD camera adopts frame transfer type architecture, which has fast conversion speed, high quantization precision and high quantum efficiency. Accurate understanding of the camera interface signal and its timing relationship, master the principle and implementation of its image data transmission card, can greatly expand the application field of digital CCD camera, improve the flexibility of the application system. This article refers to the address: http:// 1 digital CCD camera and its interface technology The CA-D7-1024T digital CCD camera manufactured by DALSA is used in this system. The camera is a frame transfer type CCD camera with a spatial resolution of 1024 x 1024 pixels and a single pixel size of 12 μm x 12 μm with a 100% fill factor. The camera uses internal double sampling (CDS), vertical reversal (VAB) and other technologies to greatly improve the imaging quality of the camera. The camera outputs sampled, quantized data with a quantization accuracy of 12 bits and a maximum frame rate of 8.4 Hz, an electronic shutter. The camera is internally composed of CCD image sensor, driver, timer, A/D conversion and other modules. Its interface signals are divided into two categories: user bus interface signals and data bus interface signals. User bus interface signals include: • EXSYNC trigger frame readout signal is a must-have signal. When EXSYNC is fixed low, the camera outputs image data at the maximum frame rate; when EXSYNC is positive or negative, its falling edge triggers frame readout. • PRIN pixel reset signal, which is an optional signal. The pixel is reset between the two EXSYNC assertions (discharges the accumulated charge), thereby reducing the effective exposure time. PRIN is active low and begins effective exposure on its rising edge. If PRIN is fixed high, the integration time is maximum; if PRIN is fixed low, the detector does not collect any image information. · BIN  cell merge signal, also an optional signal, can control cell merging. Combining pixels reduces the spatial resolution of the camera, but it increases the sensitivity of the detector to light. The BIN signal is active high and is tied low when not in use. The above signals are generated by the application system and sent to the camera, which provides a means for the application system to set the working mode of the camera according to needs. The data bus interface signal is the camera output signal, including: DATA0~1112-bit data bus. DATA0 to 11 are 12-bit image data output by the camera and corresponding to the gray level of a certain pixel of the target. · STROBE  cell clock signal. STROBE is the cell clock of image data. Its frequency is the same as the data rate, even if the data is invalid, STROBE is still alternating. In order to obtain valid image data, the transfer card should perform data latching on the falling edge of STROBE when FVAL and LVAL are high. · FVAL  frame sync signal. A high FVAL indicates that the camera is outputting a frame of valid data. · LVAL is synchronized. When FVAL is high, a high LVAL indicates that the camera is outputting a valid cell line. Between two active lines, LVAL goes low to skip a few invalid cells, and the number of cells skipped depends on the camera model and pre-trigger settings. The image data transmission card uses these interface signals to realize the control of the camera and the capture operation of the image data. In order to improve the anti-jamming capability of the signal, all of these interface signals are transmitted between the digital camera and the image transmission card in a differential manner according to the RS422 specification. The transmission cable is a 100Ω shielded twisted pair. Figure 1 shows the timing relationship between camera interface signals. When PRIN transitions from low to high, the camera begins to exposure. After the set exposure time is reached, the EXSYNC signal goes low and the frame readout is triggered. At this time, the camera first performs frame transfer. When the frame transition is over, the output signal FVAL starts from a low to high to indicate a valid data frame, and LVAL changes from low to high to indicate that the camera is outputting a valid pixel row. When FVAL and LVAL go low again, it means that one frame of data output is over, and the second trigger frame read can be started (making EXSYNC valid). The second exposure can be performed after the end of the first frame transfer and before the start of the second frame readout, and the exposure time is adjustable within a certain range. 2 Digital CCD camera image data transmission card design and implementation In the application system, the main task of the digital CCD camera image data transmission card is to generate the input signal required for the camera to work, interpret the camera output signal, make the camera work in the electronic control mode, and capture the camera output in real time and correctly. Image data, establishing a hardware transmission channel between the camera and computer memory. In order to adapt to the continuous improvement of data transmission rate of digital CCD camera, the early ISA bus-based image data transmission card is gradually transitioning to the PCI bus-based transmission card. 2.1 Image Data Transfer Card Circuit Description The block diagram of the image transmission card designed and developed by the author for the DALSA CA-D7-1024T digital CCD camera is shown in Figure 2. The drive conversion interface circuit performs mutual conversion between RS422 and TTL levels on the interface signal between the camera and the transmission card; the dual port RAM is a frame memory, and can be programmed to write one frame of image data output by the camera, or via a PCI bridge. Read image data to the internal memory. The frame memory can realize simultaneous exposure of multiple cameras, and the image data is written into the memory through the computer bus. The FPGA timing generator is used to generate the address lines of the dual-port RAM, the read/write control lines, and the contact signals required for the camera and the transmission card to function properly. The PCI interface chip is a bridge between the computer and the dual-port RAM and FPGA. The data and control signals are transmitted between them, and various transmission modes provided by the PCI protocol can be realized through initial setting. 2.2 FPGA timing logic generator design The image data transmission card uses the FPGA chip EPM7128SLC84-15 produced by ALTRA as the timing logic generator. It implements a 20-bit counter, a 1-bit counter, two latches, and a dozen non-standard logic gate functions through system programming (ISP). The 20-bit counter provides an address for the 1M×4Bit frame memory; the 1-bit counter is used to divide the 30MHz clock signal on the card by two to generate a 15MHz VCLK signal; the two latches respectively output the line sync and field sync signals. The logic gate is used to implement the AND, OR, and unequal logic operations of the signal. ALTERA's MAX+PLUSII programming simulation tool software can perform system programming, simulation and debugging on the FPGA chip, greatly improving the flexibility of the transmission card design and adaptability to different types of cameras, and shortening the development cycle of the transmission card. The system module is programmed in the system using the AHDL programming language. The main body of the program file is as follows: BEGIN HSYNC = lpm_ff_component2. Q0. . 0 Lpm_ff_component2. Clock = FVALT&STROBT&LVALT& GP5 # GP5&VCLK Lpm_ff_component2. Data0. . 0 = HSYNN VSYNC = lpm_ff_component3. Q0. . 0 Lpm_ff_component3. Clock = FVALT&STROBT&LVALT& GP5 # GP5&VCLK Lpm_ff_component3. Data0. . 0 = VSYNN STROO = FVALT&STROBT&LVALT&GP5  A19. . 0 = lpm_counter_component. Q19. . 0 Lpm_counter_component. Aclr = sclr Lpm_counter_component. Clock=FVALT&STROBT&LVALT& GP5 # GP5&VCLK /WE = FVALT&LVALT&STROO  /OE = FVALT FVTA = FVALT /FVTA = FVALT VCLK = lpm_counter_component1. Q0. . 0 Lpm_counter_component1. Clock = VVCLK VVCLK = CLK & GP5 2VCLK = VVCLK F1 = A19&GP5 HSYNN =A5&A6&A7&A8&A9&GP5 VSYNN = A14&A15&A16&A17&A18&GP5 END 2.3 Multi-layer high-speed printed circuit board design The printed circuit board of the image data transmission card developed by the author is designed as a four-layer board. In addition to the top layer and the lower layer, the power supply and the ground layer are separately designed, which is a basic requirement based on the PCI bus board. In addition, since the data, address and control signals on the card are mostly high-speed signals, the following points must be noted when designing the printed board: The maximum trace length of the PCI bridge pin is limited to 1.5 inches, the CLK signal trace length is limited to 2.5 ± 0.1 inches, and only one load is connected; The no-load characteristic impedance (Z0) of the shared PCI signal line on the board should be controlled at 60-100 Ω; · PCI control signals should consider pull-up resistors; • Each power supply pin must be decoupled to ground to handle the impact of the switching current. Generally, a 0.01μF high frequency decoupling capacitor is connected across; · The capture card should comply with the limit of the maximum pin capacitance of less than 10pF; • The shared PCI signal is on the board and can only carry one load. Based on the in-depth study of the requirements of the digital CCD camera interface, according to the above design principles, the image data transmission card based on the PCI bus and suitable for simultaneous exposure of multiple cameras is successfully developed. The card successfully passed the debugging in the prototype of the airborne multi-band polarization imaging system. The test data shows that the image data transmission card can meet the design requirements of the system. 35Kv Steel Pole,Stainless Steel Poles,steel pole price,Galvanized Metal Posts Jiangsu Baojuhe Science and Technology Co.,Ltd. , https://www.galvanizedsteelpole.com
November 22, 2023